Integrated circuit devices are formed from a large number of interconnected integrated circuits. The active elements or transistors which make up the integrated circuits are typically fabricated in the lower layers of the integrated circuit device. Above the transistors, a number of metal layers are formed. The metal layers are used as power lines, which provide power to the integrated circuits, and as signal wires, which interconnect the integrated circuits and provide signal transmission therebetween.
During integrated circuit design, design engineers pay particular attention to the allocation of the metal layers between power lines and signal wires in order to ensure adequate power while achieving the most densely packed signal wiring. In a typical design approach, a software model containing the integrated circuits of the device is first developed using well known design techniques. The design engineer then develops a power line layout or grid for the modeled integrated circuit device. The power line layout is typically designed with moderate conservatism in order to ensure adequate power for the device. Next, signal wires are added to the integrated circuit model based on the layout of the integrated circuits on the device as well as the power line layout. Typically, the signal wires are automatically routed using software routing tools (hereinafter "routers"), such as G-Route.TM. by Cadence Design Systems, Inc.
The routing of signal wires typically includes two phases: a global phase and a detail phase. In the global phase, the router divides the entire integrated circuit device into squares or tiles, each of which contain a number of tracks in which signal wires may be routed. Using the global tiles the router generates, paths which interconnect the integrated circuits. FIG. 1A illustrates an exemplary portion 100 of an integrated circuit device divided up into tiles 110 and having two circuits A and B interconnected by a global path 120. In the detail phase, the router makes detailed signal wire routes between integrated circuits based on the global paths and the tracks of the tiles therein. FIG. 1B illustrates a signal wire 130 interconnecting circuits A and B after the detailed phase of wire routing. In some instances, after automatically routing signal wires, some routes between circuits will remain incomplete. These incomplete routes are then typically completed manually.
The above approach places significant limitations on the scaling of integrated circuit devices. For example, should an excessively conservative amount of metal be devoted to power lines, the integrated circuits may need to be spread out in order provide room for the signal wires. Spreading out of the integrated circuits increases the size of the device and may also negatively impact performance.